My precious, fun, sexy Control Unit takes fifteen damn minutes to compile into Verilog. One little change, then I’m stuck doing actual homework for a while.
If I were comfortable enough with Verilog (ha!), I’d be better off making the changes directly to the Verilog file, then running StateBench to test it.
If I can’t get through basic testing before midnight, tonight, I may be learning myself some Verilog so I can do just that.
It’s not the time that bothers me so much as the brain-switching from DISCO to Comp Arch to Probability to Comp Arch to… Yeah. Bleh.